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Major CADSTAR Enhancements...Any Design Rule Error in the Design Rule Check Report can be marked as accepted by the user. This allows the user to concentrate on other errors in the design. Pin Identifiers and Alphanumeric Pin Names Pin numbers in components have been replaced by pin identifiers, which support alphanumeric characters and non-consecutive numbers. Pin names can also now start with numeric characters and can be purely numeric. Autoroute Schematic Connections when Moving When moving design items on a schematic design the connections will be dynamically autorouted to avoid crossing other connections and symbols. The BGA and Staggered Grid wizards have been improved to allow additional pin configurations to be specified. Additional parameters have been added to specify:
The Drill Table has been updated to include an extra column that is user-defined, allowing for any extra information to be added to the table. The visibility of columns within the table can now be controlled to give the user more flexibility over what information is displayed. CADSTAR also now provides a way to suppress the most frequent Drill Letter on a layer-pair basis, to reduce clutter in designs. Name Range By Sheet is a new setting for schematic designs that allows users to manage component names from the start of the design cycle. The user establishes a defined range for each sheet and all new symbols will then be added with a name appropriate for the range of the sheet. An active report is added that lists Name Range By Sheet settings and any symbols whose name suffix is not within the defined range of the sheet they are on. Positional Rename has been modified to provide a mechanism to quickly rename any symbols that are not correctly named. The ability in Component Editor to rename pads has been enhanced to give more control over the naming used. This is in line with the support of alphanumeric pin names. Naming may be applied numerically or alphanumerically and the directions (horizontal or vertical) in which alphabetical and numerical identifiers are applied can be controlled. CADSTAR now allows colours to be applied to Vias by their Layer Pair so all Vias of a certain Layer Pair can be displayed in the same colour. This allows for a way to quickly see which Vias correspond to which Layer Pair. Other CADSTAR Enhancements...Consistent Fixed Flag on Variant Components When the fixed flag is changed on a variant component/symbol all fixed flags of its variants will also be changed. Customisable Edit Part Preview Windows The Library Editor now retains its splitter positions between calls to the Edit Part Definition window. Also, the layout of the splitters can be changed between vertical and horizontal. Enhancement to 'Output Not-Fitted Items' Export Option The export of not-fitted component's sub-types, for PCB and schematic has been enhanced and now for both design types using this option will allow manufacturing output to display not-fitted component sub-items in a specified colour. Alternatively it can be unchecked and these items will not be displayed in the manufacturing output. When using the Library Searcher to add a part to a design or to select a part in the Add Part dialog it is now possible to select a specific alternate of the part to be used. The preview window has drop-down lists of the possible alternates that can be selected. A default alternate is selected initially. Manufacture Design with Error Warnings When exporting a design out for manufacture and the design contains DRC errors, a warning message is displayed and the user is asked to confirm before proceeding. This is in order to reduce the risk of exporting data for manufacture that contains design rule errors. There is now an option to change the way items are displayed, by having them drawn to an off-screen memory buffer before the image on the canvas is updated. This is in contrast to the traditional method of building up the display incrementally, such that each item can be seen being drawn. On certain operating system and graphics hardware combinations this new method can provide a significant performance improvement. It is now possible to add a design origin to Schematic and Documentation symbols, making the process of creating and modifying these symbols easier. This is now consistent with component symbols, where a design origin could already be specified. Retain Net Name on Owner Deletion Unintentional loss of a Net Name is now protected against by ensuring that when the owner of the last visible signal name is deleted the name is created on a remaining node. The way signal names are placed has been updated to place the name at the most important node on a connection. P.R.Editor XR Enhancements...P.R.Editor also provides support for colouring vias based on the layer-pair that they use as an alternative to colouring them based on the layer they are on. This is consistent with the same feature that has been added to CADSTAR Design Editor. There is a new option for Testpoints to treat them as a node for the purpose of Node to Node selection. This will allow, for example, the unrouting of track between Testpoints without unrouting the entire track and losing the Testpoint. P.R.Editor XR HS / SI Verify Enhancements...The SPICE import now supports automatic generation of the device in the Simulation Library on import. It also now has support for more complex SPICE files to be imported. Meaningful Names for new scenarios Scenario creation now offers a name for the new scenario, which is based on the selected design item. When multiple items are selected a generic scenario name will be offered. As before, it is possible to enter any custom name. The Extended Results dialog in Configuration Editor has been enhanced to improve the way modal impedances in multi-conductor configurations are displayed Using the skew groups wizard is no longer limited to a single source-to-receiver pair per electrical net. SI Simulator Kernel Improvements The SI Simulator kernel has been improved for performance. The main improvements are in the area of the DC pre-Analysis, particularly for cases including S-Parameter models or large circuits. In addition to this, the progress bar displayed during interactive SI Simulation now indicates the steps of the DC pre-Analysis. This enables the user to additionally cancel the simulation in this process step. Base library buffer models have been optimized for simulation stability and performance. System connectors can now be created from components that are affected by design variation, allowing greater flexibility during the early design of a system. |
