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With key functionality in many cases commoditized, the success or failure of wearables is increasingly determined in the early stages of the PCB and mechanical integration process where requirements are translated into practical design decisions such as how functions are mapped to PCBs and PCBs are integrated into the enclosure.
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In the final installment of this blog series, you can learn how to use build-up layers and premium FPGAs to deal with the signal integrity challenges arising from high-speed signals in a 3D design capture world.
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This is the second in my series of blog posts looking at the challenge of maintaining PCB signal integrity with now-common ultra-high speeds and growing adoption of PCB design environments to design in true 3-D. Today I focus on vias and the use of return vias to overcome the issues highlighted in Part 1.
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Ultra-high signal speeds demand detailed consideration of the third dimension in PCB design, including via structures and layer stacks. Today I’m going to focus on the challenge. In my two subsequent posts I’ll be reviewing what PCB designers can do to meet that challenge.
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In my previous post in this series about effectively reusing design modules to increase product quality and decease development time, I challenged you to think about how well you’re making use of existing design modules and why getting better at this could be a competitive differentiator.
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In this two part series of blog posts, I’m going to be looking at reuse with modular design in PCB development, and how you can streamline your methodology to reduce design time, reduce design errors and increase product quality.
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A company’s IP is often the basis for its competitive advantage. Without IP management or protection, your new product can be cloned by a competitor or an unknown third party. IP protection laws vary across the globe so the best approach is to protect your IP before it leaves your company.
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As Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route to those constraints. This question arose recently when we were asked to create a common style of DDR3 design for training, and we tried mining the web for detailed information on PCB constraints. There had to be something out there, we thought.
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Last week I introduced you to the concept of S-Parameters, and now I’m going to explain a bit more about measuring them and simulating with S-Parameter models.
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I’d like to explain to you in straightforward terms what S-Parameters are and why they’re so useful. When I say “straightforward”, I mean that in a technical sense, but this is a specialised area. If you’re not designing high-speed PCBs, or you don’t know much about signal integrity, you might want to tune out now.