semiconductior360 LIVE 2021

Iyad Rayane is Zuken’s European Technical solutions architect for the 3D-IC/Advanced Packaging and Co-Design Environment, focusing on Zuken’s Co-Design flow and Advanced Packaging solution with CR-8000. He holds an engineer diploma and a Master’s degree in microelectronics from the poly-technical institute in Grenoble, France. He has more than 20 years of experience in the semiconductor field where he worked around 11 years as application engineer at Mentor Graphics for SoC design on advanced process nodes. Prior to Mentor Graphics, he worked as EDA engineer at ST Microelectronics developing RF and mixed signal design flows for big design houses. Iyad started his career in a startup in Grenoble area specialized in the Mems design and modeling. He is author and co-author of many scientific publications in international conferences.

March 16, 15:00 CET (16:00 IST)

As design complexity increases with 3DICs and time-to-market becomes a critical component in the automotive, wearables and IoT segments, reducing design cycle time while maintaining accuracy of analysis has become all the more important. To address this, a system level co-design approach in step with multi-physics analysis is presented. To mitigate errors due to manual exchange of data between various engineering teams spread across chip, package and board with design and analysis adding further level of exchange, a design flow incorporating simplification at the layout level is shown. The flow enables various levels of simplified models to be used, wherein data transfer between the complex 3D structured in layout to the thermal analysis tool is automated. The efficacy of the model simplification is verified through a test case showing comparable results for the simplified and full models.

Co-Author
Koga Kazunari, Zuken, Japan