DDR5 is the latest generation of memory in development, doubling the peak data rate to 6400 MT/s (compared to DDR4). With great technical ambitions come much tighter specifications for system PCB designers; Especially when faced with channel loss, skew, reflections and crosstalk, all of which become much more significant at higher frequencies. In fact, PCB design margins are so minimal that DDR5 introduces equalization on the commodity DRAM chips, for the first time.
Hardware engineers do have options though, as tools and knowledgeable partners in the industry can help to make their first design a success. In this joint webinar with Keysight, we will explore a predictive, productive and insightful workflow, to get to an optimal design, that performs to the target speed grade, reliably. We’ll begin with pre-layout simulation to explore design choices, then transition to constraint-based high-speed routing in Zuken CR-8000. The design will then be verified by Electromagnetic (EM) simulation and system simulations in Keysight ADS, in order to build confidence in the final DDR5 design.
