Conception conjointe de puce, empaquetage et carte 2D/3D

Design Force chip, package and board co-design provides a technology-rich and device-rich design environment for implementing traditional and advanced node design structures like die + package + PCB, SiP, PiP, and interposer + TSV.

Design Force Chip-Package-Board Co-Design provides a single environment solution for maximum system optimization.

Design Force supports integrations to best-in-class tools from partners such as ANSYS, AWR, Agilent and Synopsys for RF, Full Wave FD/TD, power integrity, and thermal extraction and analysis. This allows designers to address key issues early in the design process.

Post layout extraction of single and coupled (crosstalk) routed traces; What-if analysis; Cross-section view for traces.

A simulation environment for post layout signal integrity simulation.

A powerful PCB-FPGA co-design environment that enables exchange of I/O and constraint information between PCB designs and FPGA designs.

A simulation environment for Power Integrity (AC impedance and de-coupling impact, DC voltage drop, current analysis) and electro-magnetic interference (EMI full board screening, differential mode, common mode, power bus noise).

Fast and easy check of the current density of a layout structure towards a given maximum.