CADSTAR SI Verify

Signal Integrity – CADSTAR SI Verify

As more designs incorporate high-speed technologies and involve integrated circuits (ICs) with rapidly increasing fast edge rates, the need for signal integrity analysis has become a vital part of the product development cycle. Signal quality is an important factor in the performance of the overall product, so the need to analyze crosstalk effects, over/undershoot, propagation delays and the evaluation of different termination schemes can help identify problems early in the design process, and avoid unnecessary design failures and costly iterations.

High-speed interfaces such as DDRx and PCI Express demand complex timing requirements that cannot be resolved by applying traditional rules of thumb to secure effective signal quality. CADSTAR SI Verify offers a complete concurrent and post-layout signal integrity solution that enables engineers, layout designers and specialists within a development team to collaborate, organize, constrain, and verify their design in a seamless process. This helps them work more effectively, minimize costs, and improve overall time to market.

Top features and benefits

• Integrated within CADSTAR High Speed Design suite for concurrent and post-layout SI analysis and constraint verification
• Accurate transmission line analysis for fast calculation of reflection and crosstalk effects
• Embedded simulation model library includes standard IC models and an IBIS 5.0 parser
• Support for eye diagrams, frequency domain/S-Parameter simulations, and parameter sweeps
• Time domain analysis supports frequency-dependent “skin effect” and Ohmic losses for accurate simulation into the GHz domain
• Perform virtual measurements at the IC package pin or directly on the silicon die
• Frequency domain simulation supports S-Parameter and transmission line impedance, with the option to export S-Parameter data in Touchstone format