How to be First to Market with DDR5!

How to be First to Market with DDR5!

Webinar On-demand

DDR5 is the latest generation of memory in development, doubling the peak data rate to 6400 MT/s (compared to DDR4). With great technical ambitions come much tighter specifications for system PCB designers; Especially when faced with channel loss, skew, reflections and crosstalk, all of which become much more significant at higher frequencies. In fact, PCB design margins are so minimal that DDR5 introduces equalization on the commodity DRAM chips, for the first time.

Hardware engineers do have options though, as tools and knowledgeable partners in the industry can help to make their first design a success. In this joint webinar with Keysight, we will explore a predictive, productive and insightful workflow, to get to an optimal design, that performs to the target speed grade, reliably. We’ll begin with pre-layout simulation to explore design choices, then transition to constraint-based high-speed routing in Zuken CR-8000. The design will then be verified by Electromagnetic (EM) simulation and system simulations in Keysight ADS, in order to build confidence in the final DDR5 design.

What you will learn:

  • The main differences of DDR5 to previous generations
  • Why pre-layout simulation is necessary to arrive at an optimal design (using Keysight PathWave ADS)
  • How to use constraints in Zuken CR-8000 to setup routing quickly
  • How to estimate crosstalk in Zuken CR-8000
  • What is important to know about accurate Electromagnetic model extraction of the PCB (using SIPro in PathWave ADS)
  • Performing system level simulations to determine Signal Integrity and reliability of a design

Who should attend:

  • Technical and electrical design engineers
  • Engineering managers
  • PCB designers
  • Academic Researchers
  • Students

Presenters:

  • Lance Wang, Solutions Architect, SOZO Center, Zuken Inc.
    Lance Wang is a Solution Architect supporting Zuken CR-8000 for High-Speed PCB designs. Prior to Zuken, Lance was the founder of IO Methodology and PCB SI product manager in Cadence Design Systems. Lance attended the programs of MBA in Technical Marketing and MS in Computer Engineering from Boston University and BS in Microwave from Shanghai University of Science and Technology (PR China). Lance also serves as the Vice-Chair of SAE/IBIS Open Forum since 2008.
  • Stephen Slater, Product Manager for SI & PI Simulation
    Stephen Slater leads the SI & PI product planning and marketing team at Keysight PathWave Software Solution.  Over the last decade Stephen has been working closely with customers using Keysight’s Advanced Design System (ADS), for high-speed serdes channel simulations, DDR simulation and Electromagnetic simulation for PCB applications.  Prior to joining Keysight, Stephen graduated from Griffith University (Australia) with a BS in Electronic Engineering (First Class Honors), and a BS of Information Technology.
  • Tunir Dey, Application Engineer, SOZO Center, Zuken Inc.
    Tunir Dey is currently serving as an Applications Engineer for CR-8000 product at Zuken Inc. Tunir is working closely with customers in system level schematic design using Design Gateway, PCB layout design using Design Force, constraint management, topology development, SI, PI and EMC analysis. Before joining Zuken, Tunir used to serve as a Product Engineer intern in one of the major EDA company and was responsible for RF, Microwave, high frequency and high-speed simulation. Tunir graduated from Purdue University with an MS in Electrical Engineering (RF and Microwave) and an MBA in Finance from Indiana University.

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