DDR4 Design Hands-On Workshop

DDR4 represents the fourth generation of data rate memories. DDR4 memory devices (and their low-power version LP-DDR4) can be found in computer and IT applications and almost all advanced electronic products. Implementing DDR4 technology requires delicate and specific PCB design constraints to ensure proper operation.

What You Will Learn

In this workshop, participants will learn how to implement DDR4 memory interfaces using Zuken’s CR-8000 from the conception phase to the physical place and route and validation for SI and PI.

We will cover front-to-back constraining for proper impedance values, the extraction of constraints from vendor documents and their implementation into the schematic, the constraints-driven technology definition, the placement of DDR4 components, and the routing against these constraints. Finally, participants will learn how to perform an analysis of the DDR4 interface for various signal and power-integrity effects.

Prerequisites

Attend the session called DDR4 Design Hands-On Workshop Foundations (June 7 at 11:00 am), where we will cover these topics to prepare you for the workshop.

• Basic knowledge of DDR4 technology and terminology
• Understanding of the tools available within CR-8000 to address DDR4 tasks

Learn How to Implement These DDR4 Constraints and Incorporate them into a Design.

• Define a reference layer and understand return paths
• Rules to ensure proper signal integrity, impedance, and skew
• Placement of decoupling capacitors
• Define spacing between memory signals and other parts of the PCB
• Terminating address and control signals and defining the best settings for your desired application, DDR4 speed grade, and memory configuration.
• Adhere to relevant JEDEC guidelines and manufacturer recommendations to ensure compatibility and proper operation of the memory modules.
• Validate all of the above via SI/PI simulations.